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SystemVerilog - Unified Hardware Design, Specification, and Verification Language
60.60 Standard published
SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual
60.60 Standard published
Standard for the common test interface pin map configuration for high-density, single-tier electronics test requirements utilizing IEEE Std 1505™
60.60 Standard published
Strategic principles for future IEC and ISO standardization in industrial automation
90.93 Standard confirmed
Smart manufacturing standards map (SM2) — Part 1: Framework
60.60 Standard published
Smart manufacturing standards map (SM2) — Part 2: Catalogue
60.60 Standard published