0

IEC 62530:2021 ED3

SystemVerilog - Unified Hardware Design, Specification, and Verification Language IEC 62530:2021 ED3

Publication date:   Jul 26, 2021

General information

60.60   Standard published   Jul 26, 2021

IEEE

TC 91

International Standard

25.040.01   Industrial automation systems in general | 35.060   Languages used in information technology

Buying

Published

Language in which you want to receive the document.

Scope

IEC 62530:2021(E) provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.
This edition corrects errors and clarifies aspects of the language definition in IEEE Std 1800-2012.1 This revision also provides enhanced features that ease design, improve verification, and enhance cross-language interactions.
This publication has the status of a double logo IEEE/IEC standard.

Life cycle

PREVIOUSLY

WITHDRAWN
IEC 62530:2011 ED2

NOW

PUBLISHED
IEC 62530:2021 ED3
60.60 Standard published
Jul 26, 2021




Access Genorma App Everywhere

Get fast and easy access to top European and International standards (EN, ISO, IEC) via your mobile phone, tablet or the web.

Google Play App Store Web Version