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IEC 60191-6-5 ED2

Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA) IEC 60191-6-5 ED2

General information

10.98   New project rejected   Oct 24, 2013

IEC

TC 47/SC 47D

International Standard

Life cycle

PREVIOUSLY

PUBLISHED
IEC 60191-6-5:2001 ED1

NOW

ABANDON
IEC 60191-6-5 ED2
10.98 New project rejected
Oct 24, 2013




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