HD 524 S1:1989

Microprocessor system bus for 1 to 4 byte data

Scope

This standard describes a high performance backplane bus for use in microprocessor based systems - This parallel bus supports single and block transfer cycles on a 32-bit non-multiplexed address and data highway - Transmission is governed by an asynchronous handshaken protocol - The bus allocation provides for multiprocessor architectures - This bus also supports inter-module interrupts for facilitating quick response to internal and external events - The mechanics of the boards and chassis are based on IEC Publication 297: Dimensions of Panels and Racks