Describes a high-performance backplane bus for use in microprocessor bases systems. This parallel bus supports single- and block-transfer cycles on a 32-bit non-multiplexed address and data highway. Transmission is governed by an asynchronous handshaken protocol. The bus allocation provides for multiprocessor architectures. This bus also supports inter-module interrupts for facilitating quick response to internal and external events. The mechanics of the boards and chassis are based on EN 60297. Note: -1.This bus is similar to the VME bus. 2.For the price of this publication, please consult the ISO/IEC price-code list.
WITHDRAWN
HD 524 S1:1989
PUBLISHED
EN 60821:1994
60.60
Standard published
Jun 2, 1994
PUBLISHED
EN 60821:1994/corrigendum Aug. 1994