90.93 Standard confirmed Jul 13, 2018
ISO/IEC
ISO/IEC JTC 1/SC 25 Interconnection of information technology equipment
International Standard
35.100.30 Network layer
The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-toboard communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.
PUBLISHED
ISO/IEC 18372:2004
90.93
Standard confirmed
Jul 13, 2018
ABANDON
ISO/IEC NP 18372