IEC 62142:2005 ED1

Verilog (R) register transfer level synthesis IEC 62142:2005 ED1

Publication date:   Jun 27, 2005

Scope

Defines a set of modeling rules for writing Verilog®
HDL descriptions for synthesis. Adherence to these rules guarantees the interoperability of Verilog HDL descriptions between register-transfer level synthesis tools that comply to this standard. The standard de.nes how the semantics of Verilog HDL
are used, for example, to describe level- and edge-sensitive logic. It also describes the syntax of the language with reference to what shall be supported and what shall not be supported for interoperability.