IEC 61691-6:2009 ED1

Behavioural languages - Part 6: VHDL Analog and Mixed-Signal Extensions IEC 61691-6:2009 ED1

Publication date:   Dec 14, 2009

Scope

IEC 61691-6:2009(E) Defines IEC 61691-6/IEEE Std 1076.1 language, a hardware description language for the description and the simulation of analog, digital, and mixed-signal systems. The language, also informally known as VHDLAMS, is built on the IEC 61691-1-1/IEEE 1076 (VHDL) language and extends it to provide capabilities of writing and simulating analog and mixed-signal models.