IEC 61691-3-3:2001 ED1

Behavioural languages - Part 3-3: Synthesis in VHDL IEC 61691-3-3:2001 ED1

Publication date:   Jun 28, 2001

Scope

This standard supports the synthesis and verification of hardware designs, by defining vector types for representing signed or unsigned integer values and providing standard interpretations of widely used scalar VHDL values. Includes package bodies, as described in annex A, which are available in electronic format either on a diskette affixed to the back cover, or as a downloadable file from the IEC Web Store.