IEC 61523-2:2002 ED1

Delay and power calculation standards - Part 2: Pre-layout delay calculation specification for CMOS ASIC libraries

Publication date:   May 17, 2002

95.99 Withdrawal of Standard   Jun 1, 2011

General information

95.99 Withdrawal of Standard   Jun 1, 2011


TC 91 Electronics assembly technology

International Standard

35.240.50   IT applications in industry



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Applies to CMOS ASIC libraries which contain cell based primitives and memories to be used during the pre-layout design phase of logic simulation, timing verification and logic synthesis.The delay calculation method addressed in this standard consists of 1) estimation of wire capacitance 2 ) Delay calculation method based on tablelook-up. With use of DCL and SDF, this delay calculation method helps the user have a unified timing model for various EDA tools in the pre-layout design phase.

Life cycle


IEC 61523-2:2002 ED1
95.99 Withdrawal of Standard
Jun 1, 2011