Revised
Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>
WITHDRAWN
IEC 62530:2007 ED1
99.60
Withdrawal effective
May 19, 2011
WITHDRAWN
IEC 62530:2011 ED2