IEC 62530:2007 ED1

Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language

Publication date:   Nov 7, 2007

General information

99.60 Withdrawal effective   May 19, 2011

IEC

TC 91

International Standard

25.040.01   Industrial automation systems in general

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Scope

Specifies extensions for a higher level of abstraction for modeling and verification with the Verilog hardware description language (HDL). This standard includes design specification methods, embedded assertions language, testbench language including coverage and assertions application programming interface (API), and a direct programming interface (DPI)>

Life cycle

NOW

WITHDRAWN
IEC 62530:2007 ED1
99.60 Withdrawal effective
May 19, 2011

REVISED BY

WITHDRAWN
IEC 62530:2011 ED2