IEC 62530-2:2021 ED1

SystemVerilog - Part 2: Universal Verification Methodology Language Reference Manual

Publication date:   Jul 26, 2021

General information

60.60 Standard published   Jul 26, 2021


TC 91 Electronics assembly technology

International Standard

25.040.01   Industrial automation systems in general | 35.060   Languages used in information technology



Language in which you want to receive the document.


IEC 62530-2:2021(E) establishes the Universal Verification Methodology (UVM), a set of application programming
interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™. This publication has the status of a double logo IEC/IEEE standard.

Life cycle


IEC 62530-2:2021 ED1
60.60 Standard published
Jul 26, 2021